MIPS Technologies Updates Processor IP Lineup with Aptiv Series
by Ganesh T S on May 10, 2012 8:55 AM ESTARM has been making waves over the past two years with plenty of processor and graphics IP announcements, but they are not alone in the game. MIPS Technologies, almost as old as ARM itself, also licenses RISC processors. With licensees like Broadcom and Sigma Designs, they have undoubtedly held the upper hand in the home entertainment / set-top-box arena as well as the networking space. However, success in the fast-growing mobile / tablet space has been hard for MIPS to come by, thanks to ARM being well-entrenched in that market.
Today, MIPS is introducing a range of new processor IP cores in the Aptiv lineup, similar to ARM's Cortex. The members of this lineup range from small microcontroller cores to triple dispatch superscalar ones. By introducing a member at each performance level to compete directly with offerings from ARM, MIPS has made its move in the processor IP battle.
MIPS last introduced a new processor IP core back in September 2010, the MIPS 1074K Coherent Processing System. Between September 2010 and now, ARM officially announced the Cortex-A15 (well after TI had announced an SoC based on it) and Cortex-A7. In the preceding year, the Cortex-A5 and the Cortex-M4 had been launched. The Aptiv series from MIPS introduces members which compete against each of these offerings.
Throughout the briefing, MIPS stressed that the standard DMIPS/MHz/core was not a reliable benchmark. Instead, they promoted CoreMark in which their cores performed better than ARM's offerings. CoreMark is comprised of small and easy to understand ANSI C code with a realistic mixture of read/write operations, integer operations, and control operations. CoreMark has a total binary size of no more then 16K using gcc on an x86 machine (this small size makes it more convenient to run using simulation tools). We do agree with MIPS that it could be a better measure of L1 cache and branch prediction performance. Unfortunately, we don't have reliable CoreMark data for the upcoming Cortex-A15, and hence, will be using DMIPS/MHz/core as a rough performance comparison metric in the rest of the piece.
The Aptiv series being launched today consists of three families, the proAptiv, interAptiv and microAptiv. While proAptiv and interAptiv come in multi-core variants (with up to 6 for the former and 4 for the latter), the microAptiv family members are all single core.
The following tables presents the various MIPS and ARM processor IP cores available for licensing in order of their performance. Note that multiple generations of processors are presented in the table. The Cortex-A,R & M series cater to the application processor segment, real-time processing segment and the microcontroller segment respectively. They are matched field for field by the proAptiv, interAptiv and microAptiv series being launched by MIPS today.
| MIPS and ARM High End IP Cores in Order of Performance | ||
| MIPS | DMIPS/MHz/core | ARM |
| proAptiv | 3.5 | Cortex-A15 |
| 2.5 | Cortex-A9 | |
| 1074K | 2.03 | |
| 74K | 2.0 | Cortex-A8 |
| 1.9 | Cortex-A7 | |
| 1.57 | Cortex-A5 | |
| M24K | 1.46 | |
| 1.24 | ARM11 | |
| 1.14 | ARM9 | |
In terms of processor IP cores catering to real-time applications where high reliability (such as ECC support for the internal caches) and low power footprint is also required, the interAptiv family and the Cortex-R series go head to head. That said, MIPS also targets interAptiv family members as alternatives for Cortex-A5 / A7 / A9. However, the target market for the Cortex-R series and interAptiv series are similar (wireless baseband / automotive applications such as safety and powertrain control etc.)
| MIPS and ARM Mid-Range IP Cores in Order of Performance | ||
| MIPS | DMIPS/MHz/core | ARM |
| 2.5 | Cortex-R7 | |
| interAptiv | 1.7 | |
| 1.66 | Cortex-R5 | |
| 34K | 1.62 | Cortex-R4 |
| 1004K | 1.5 | |
| 24K | 1.46 | |
In the microcontroller class processor IP cores, the microAptiv series is pitted against the Cortex-M series.
| MIPS and ARM Microcontroller Class IP Cores in Order of Performance | ||
| MIPS | DMIPS/MHz | ARM |
| microAptiv | 1.57 | |
| M14K | 1.5 | |
| M4K | 1.3 | |
| 1.25 | Cortex-M3 / Cortex-M4 | |
| 0.9 | Cortex-M0 | |
| 0.8 | Cortex-M1 | |
In the next few sections, we will look at the architectural details of the newly introduced processors.
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sicofante - Thursday, May 10, 2012 - link
What's the meaning of IP here? Thanks.Homeles - Thursday, May 10, 2012 - link
Intellectual Property.http://en.wikipedia.org/wiki/Semiconductor_intelle...
SydneyBlue120d - Thursday, May 10, 2012 - link
Is there something like Mali, PowerVR and so on? And what about Cell modems (LTE and so on)? Thanks.Arnulf - Thursday, May 10, 2012 - link
This is precisely why AMD should be the buyer of MIPS. They can contribute their (ATI's) GPU expertise and AMD's with hybrid processing ... this would be a killer combination.quadrivial - Thursday, May 10, 2012 - link
I agree that AMD and MIPS could be a great combination. I don't know if they could outbid China.The Chinese scientists who started the first (or at least the first to make tech news headlines over here) major Chinese-designed processor had the pick of any architecture they wanted (they weren't paying licensing fees anyway) and they still chose MIPS for the Loongson processors (which are now in devices ranging from small consumer devices to a petaflop supercomputer).
Penti - Thursday, May 10, 2012 - link
AMD/ATi already sold their mobile GPU business to Qualcomm and Broadcom respectably and has none left. They couldn't contribute a great deal here. As they already did to the field. These chips and MIPS Tech itself doesn't compete for the mobile space and any third party building such solutions will use basebands with ARM-cores and normal third party Silicon-IP GPUs. AMD also got rid of their MIPS-based network processors a good while ago. Those building MIPS network processors also do their own architectures (designs) and only license the ISA/Patents. They do things like 16-core 64-bit MIPS processors. Sigma Designs is one company that uses MIPS IP-cores with PowerVR graphics. Some also use Vivante IP/synthesizable GPUs. No different to ARM here except maybe less choice in the market and that it is up to Qualcomm or Broadcom to ship cores with Adreno or Broadcom Videocore/Xilleon. They won't be delivered as IP cores.Also while Broadcom and Qualcomm greatly build on and enhanced their custom design (gpus) from AMD designs that where not exactly Radeon based but other custom designs to develop them into to highly developed and fast gpus, for example nVidia didn't really do that by building "geforce-based" gpus on Tegra where it is greatly under powered and the wrong design for mobiles pretty much. AMD gpus would be disastrous to scale down too. Plus they can sell x86/x64 CPUs / APUs with AMD GPUs for the Android tablet market or Tablet PC market already. They have no reason to go ARM or MIPS (again) just as Intel has no reason to go back to ARM (XScale). They might for servers, but not clients. They can deliver other solutions based on their existing tech there.
Guspaz - Friday, May 11, 2012 - link
MIPS doesn't make the SoC, just the CPU. There's nothing stopping anybody from putting a PowerVR GPU into an SoC with a MIPS CPU.Think about it this way: ARM makes the Cortex A9, but they don't make any chips. nVidia makes the Tegra, TI makes the OMAP, Samsung makes the Exynos, Apple makes the A series, etc. The same thing is true here with MIPS. They just give you a set of blueprints for a CPU and you make it yourself.
sheh - Thursday, May 10, 2012 - link
I had the impression all those routers were running ARM. What's that about no multithreading on ARM? In terms of something like Intel's Hyperthreading?BTW, "upto" -> "up to".
Arnulf - Thursday, May 10, 2012 - link
Most use MIPS chips (something along the lines of an R4000 relative).Jaybus - Thursday, May 10, 2012 - link
Yes, I believe so. ARM has only test-and-set, etc primitive instructions for atomic operations, meaning the OS is essentially performing all aspects of multithreading and context switches are expensive. Unlike x86, it has no hardware allowing for fast context switching.