Supermicro To Offer Reduced Memory Xeon Scalable

With big chips come big responsibility. One of the key elements of a big chip is its capability and connectivity, and there is always a big expectation that all of those features have to be used in every deployment. Whenever we talk about the LGA2066 consumer products built on mini-ITX reduced size platforms with only one PCIe slot, comments always pour in about why a user should buy a system that doesn’t use all the features. Well, take a look at the server space, where processors used for Compute typically ignore the PCIe side of the equation completely. Now Supermicro has gone one further and applied it to the server space.

This new implementation from Supermicro offers customers a Xeon Scalable blade server, the 6029TR-HTR, designed for a dual socket deployment, with only four memory channels per processor rather than the six that are supported.

The reason for a design like this, as Supermicro explained to me, was two-fold. Firstly, there are deployments that exist that are not memory bandwidth sensitive, or even memory capacity sensitive – these installations are only after the raw compute power of the chip. Secondly, having a reduced memory design assists with the deployment density. As shown in the images, if all six memory channels were needed, then there would be additional space between the processors due to the memory slots. Customers have been asking for this, and so a product was made.

In the consumer space, the first generation LGA2066 mini-ITX boards from ASRock did this, by only have two memory slots for dual channel memory despite that the processor could support four. There was, unfortunately, substantial vitriol about how this was limiting the system. At least in the server space at least, ultimately these products exist usually because someone has requested them.

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