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  • nandnandnand - Thursday, June 11, 2015 - link

    It wasn't it stealth mode. It was in fail mode:

    http://spectrum.ieee.org/semiconductors/memory/los...
    http://spectrum.ieee.org/nanoclast/semiconductors/...
  • Shadow7037932 - Thursday, June 11, 2015 - link

    This is pretty neat. But for DRAM replacement applications, wouldn't you need more than 100 billion PE cycles? FRAM in comparison has > 100 Trillion PE cycles.
  • freeskier93 - Thursday, June 11, 2015 - link

    The independent study said "over" 100 billion cycles, didn't say either what the results where after said 100 billion cycles. Could be they just stopped or they are still testing. Nantero is claiming near infinite cycles.
  • ianmills - Thursday, June 11, 2015 - link

    The slide says "orders of magnitude greater endurance than flash"
    Seems pretty incongruous to near infinite... sounds like a bunch of marketing fud!
  • mkozakewich - Thursday, June 11, 2015 - link

    FUD is Fear, Uncertainty, and Doubt. This is the opposite of FUD.
  • close - Friday, June 12, 2015 - link

    A mathematician and a physicist agree to a psychological experiment. The mathematician is put in a chair in a large empty room and a beautiful naked woman is placed on a bed at the other end of the room. The psychologist explains, "You are to remain in your chair. Every five minutes, I will move your chair to a position halfway between its current location and the woman on the bed." The mathematician looks at the psychologist in disgust. "What? I'm not going to go through this. You know I'll never reach the bed!" And he gets up and storms out. The psychologist makes a note on his clipboard and ushers the physicist in. He explains the situation, and the physicist's eyes light up and he starts drooling. The psychologist is a bit confused. "Don't you realize that you'll never reach her?" The physicist smiles and replied, "Of course! But I'll get close enough for all practical purposes!"

    100 billion in this particular field can be considered infinite for all practical purposes. Also the theoretical physics behind the phenomenon says the carbon nanotubes should stand basically an infinite number of cycles.
  • tuxRoller - Friday, June 12, 2015 - link

    I've never dealt with physicists who throw around the word "infinite" in the manner described.
  • ToTTenTranz - Thursday, June 11, 2015 - link

    My thoughts exactly.
    If the on/off cycle takes 2*20ns, then it'll be able to do 25 million cycles per second.

    With that speed, constantly switching the same cell would reach those 100 billion cycles within 4000 seconds. That's 1 hour and 7 minutes. Of course the controller would be made so that the cells are used in the least repetitive way, but it's still not a very encouraging number.

    I understand this can be successfully used as a replacement for flash storage, but it doesn't seem like this could be used as an unified solution for volatile and non-volatile memory.
  • azazel1024 - Friday, June 12, 2015 - link

    But what is a typical RAM write leveling per day? 100GB? 1TB? 10TB?

    8GB of this stuff, with even 8TB of NRAM writes per day works out to about 300,000 years.

    If there were even 8000TB of NRAM writes per day to 8GB of memory, that works out to 300 years.

    I am sure in a typical day of use for most computers there are at least dozens of terabytes of writes to that RAM, but multiple petabytes (dozens)? That is what would be needed to push 100 billion P/E cycles in to the range of "only a few years of endurance".

    A current typical processor and memory controller is looking at only around 20GB of writes per second to main memory. 8GB/20GB per second is .4s per full write. .4s x 100 billion is a LONG time. About 2,500 years.

    You are not doing a full memory write/erase/re-write at the maximum speed of all of the cells constantly (I don't know of any controller that is capable of writing/erasing all cells at once in RAM, NAND, etc.).
  • hazydave - Sunday, June 14, 2015 - link

    Write levelling isn't used in DRAM controllers. That's a relatively easy thing to implement for a storage controller in software. It would be more complicated to build in pure hardware for a DRAM replacement.
  • Arnulf - Thursday, June 11, 2015 - link

    "Essentially there are two nanotubes, which have high resistance when in physical contact and low resistance when separated. "

    This defines basic laws of physics.
  • Eidigean - Thursday, June 11, 2015 - link

    Yeah, scratch that, reverse it...
  • Kepe - Thursday, June 11, 2015 - link

    Yeah that caught my attention as well.
  • Kristian Vättö - Thursday, June 11, 2015 - link

    My bad, somehow I didn't pick it up during the proof-read. It's now fixed.
  • name99 - Friday, June 12, 2015 - link

    The other proof-reading problem is "Carbon nanotubes are grown from iron that would normally contaminate a clean room,"
    I assume what is actually meant here is
    (a) Carbon nanotubes are grown using an iron catalyst (or on an iron surface, or something like that). Obviously the tubes can't literally grow from iron.

    (b) because of the above ambiguity it's not quite clear in the rest of the sentence whether it is the iron that contaminates clean rooms (in which case an iron-free growth process solves the problem) or if it is the carbon that contaminates (in which case obviously things are trickier).

    I'm not trying to be a grammar nazi here, especially since many of us do not speak English as our first language, but there is a genuine confusion here about what is an interesting technical issue.
  • Ammaross - Friday, June 12, 2015 - link

    And you miss that you used "defines" instead of "defies"... :P
  • zodiacfml - Thursday, June 11, 2015 - link

    Not holding my breath on these types of storage/RAM as they could take years and by that time. Consumer devices has moved on at even more capacity. Sigh, the technology is perfect for mobile devices.
  • Kepe - Thursday, June 11, 2015 - link

    Well.. Not necessarily. NAND has a huge problem when they are scaled down; the number of P/E cycles a cell lasts lowers and lowers the smaller the fab process gets. Current 14nm MLC/TLC cells already have less than 10 000 cycles of life in them. And it'll just drop more when smaller process nodes become available. That's why these new technologies are needed. NRAM seems very promising especially because of its ability scale into such small process nodes (<5nm) without losing reliability. SSDs with regular NAND are already basically hitting the wall where they can't be switched to smaller processes because of their poor wear resistance. That means we won't be getting significantly bigger SSDs for cheaper in the future, because the only option to add capacity will be to add more NAND chips to your SSD. And that will just increase price. 3D NAND does help with capacity issues, but the NAND itself can't be made any smaller than it already is...
  • zodiacfml - Sunday, June 14, 2015 - link

    True but NAND prices will go down even more and capacity will be crucial as companies push more megapixels in photos and videos into devices.

    On a second thought, these types of technology could probably be used as low power RAM and use NAND for storage.
  • p1esk - Thursday, June 11, 2015 - link

    So, do they have a working chip? How big? How much faster than DRAM? How easy is it to mass produce? Until those questions are answered, why even bother writing an article about them?
  • Refuge - Thursday, June 11, 2015 - link

    From the article they have shown mass production, and there are some industrial companies using it.

    But they're capacities are far too small to be considered useful to any consumer.
  • p1esk - Thursday, June 11, 2015 - link

    All I see from the article is they tested an experimental chip onboard a space shuttle. If they have mass produced it, where are those chips?
    And again: how much is this memory better than DRAM or SRAM?
  • IBleedOrange - Thursday, June 11, 2015 - link

    From the EETimes article, a whopping 4Mb.
    http://www.eetimes.com/document.asp?doc_id=1326794...
  • Guspaz - Thursday, June 11, 2015 - link

    This is vapourware, so I'll believe it when I see it. This is a company that promised in 2002 to have commercial products on the market in 2004. We're now 2015 and their commercial launch is no closer than it was more than a decade ago.
  • XZerg - Thursday, June 11, 2015 - link

    I am waiting for a day when i can plug in my SoC into a device and get going... SoC would contain all devices - cpu, ram, storage, igpu, "pcie" interconnect. the "pcie" interconnect would then drive the external devices - display, usb, ...
  • gospadin - Thursday, June 11, 2015 - link

    this is about as close as you can do today, though it has USB for peripherals:

    http://www.intel.com/content/www/us/en/compute-sti...
  • mkozakewich - Thursday, June 11, 2015 - link

    Wow. It's easy to imagine ten years from now having a stacked die in your phone that acts as shared RAM and storage, in a PoP. It'll probably be cheaper than RAM at that point, and standby times would be amazing.
  • mostlyharmless - Thursday, June 11, 2015 - link

    Every 2 years or so we hear about nonvolatile memory "Just around the corner."
  • Juzam - Friday, June 12, 2015 - link

    Afaik the biggest challange with CNTs is their positioning/structuring. If I got it right, they structure the CNTs with standard lithography. How exactly helps this overcoming scaling problems?
  • Shinzon - Friday, June 12, 2015 - link

    "Technically that means NRAM is competing against current MRAM and ReRAM products for a specialized niche market that really needs high performance and non-volatility." -

    It is not a niche market. Having a computational architecture that can unify DRAM and conventional storage into one unit is the next step in computing and a needed evolution of the now very old Von Neumann architecture we still use today.

    Infact this new computer architecture will benefit everything from HPC to smartphone scale.

    HP is working on one such project with The Machine
  • name99 - Friday, June 12, 2015 - link

    Hp has given up on this with The Machine. In that the first version of The Machine that ship (if ever) will not have HW unified storage and RAM. They may still be going for a single level store at the SW level (like AS/400 aka iSeries) though that's a harder part of the problem than the HW, and not obviously useful in modern SW contexts.

    http://www.moorinsightsstrategy.com/the-machine-th...

    I don't know enough about this space to understand any more what they are going for in this computer and what the target market is. It seems to be heading towards a box with an insane amount of memory in it and some number of smallish cores --- so memcached type servers? (not much money in that) and all-RAM super-huge Oracle databases? (lotsa money in that)
  • Jaybus - Tuesday, June 16, 2015 - link

    Most processors are modified Harvard architecture, since they have a separate L1 instruction cache. Disk (SSD) storage is an i/o operation. NRAM, ReRAM, etc. doesn't change the architecture, but rather eliminates the need for i/o to/from permanent storage. Although, ReRAM also has application in neuromorphic architectures that truly are a paradigm shift.
  • BrokenCrayons - Friday, June 12, 2015 - link

    If NRAM is non-volatile and as fast as volatile memory we use today plus has infinite P/E cycles, does that mean there are implications of say, merging our present day SSD/HDD storage and RAM into a single memory repository? That'd simplify system design, improve integration, and reduce PCB space requirements/wiring complexity. It could drive costs lower and (just a total knee-jerk thought based on how each on/off state is made) lower power consumption. I might be having a ditzy moment, but is that possible? It'd be exciting if that was the case.
  • lorribot - Friday, June 12, 2015 - link

    Seems to me first use of this would be to replace battery backed write caches in the enterprise. Followed closely by disk write caches on high end NAND based storage, particularly those that have low P/E cycles.
    Alternative would be an intermediate memory to enable near instantaneous shutdown and boot up to replace standby using hibernation like methodologies.
    My only worry is whether hardware and OS support for all this will mean it takes an age for it to become available outside of proprietary/enterprise systems in a reasonable time frame.
    I offer NVMe and Thunderbolt as technologies whose widespread adoption that have been painful to watch.
  • IlllI - Tuesday, June 23, 2015 - link

    I can't get past the stupid name for the product. Really? that the best name they could come up with? sound like some comic book villian's name.

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