Thanks for posting this Ian. I know a lot of people aren't interested in this non-consumer type of news, but it is good to at least see some backend component vendor getting some spotlight. But we are still only at 64 Massive-MIMO? Which seems to be FDD Focused. I wonder how they were used in the TDD 128 x 128 Scenario.
The addressable bandwidth of the converters is 2-GHz according to their datasheets. They claim 4-GHz in their marketing buzz. 6-GHz is definitely marketing "enhancement". BTW at just a 2-GHz input signal, their effective resolution is maxed out at <9 bits which is really good, but hardly a 12b ADC or as they claim for Gen3 a 14b ADC. Funny thing is that being the only player in this game they don't need to lie in marketing campaigns, but they just can't resist temptation to tell a long tale.
While this device is definitely a game changer for ADI (wake up Analog Devices!) they do need to figure out how to scale down 30W of power which is mostly due to 16nm FPGA technology. They should migrate this to 7nm or 5nm ASAP and get to their end game for power efficiency. After that it is a race to ASIC (harden FPGA logic) for power and cost reduction.
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ksec - Friday, February 22, 2019 - link
Thanks for posting this Ian. I know a lot of people aren't interested in this non-consumer type of news, but it is good to at least see some backend component vendor getting some spotlight. But we are still only at 64 Massive-MIMO? Which seems to be FDD Focused. I wonder how they were used in the TDD 128 x 128 Scenario.Ian Cutress - Friday, February 22, 2019 - link
I think that was just the example they gave. I was told the solution scales out very easily.nathanddrews - Friday, February 22, 2019 - link
Quick, someone let ATT know immediately: 6G has arrived!sharathc - Friday, February 22, 2019 - link
Yeah. #MAGAdougw03 - Sunday, February 24, 2019 - link
Can someone explain how this chip covers 6GHz BW with only 10GSps and 2.5GSps DAC/ADC? Are they doing some tricks with undersampling?IrwinFletcher - Wednesday, March 6, 2019 - link
The addressable bandwidth of the converters is 2-GHz according to their datasheets. They claim 4-GHz in their marketing buzz. 6-GHz is definitely marketing "enhancement". BTW at just a 2-GHz input signal, their effective resolution is maxed out at <9 bits which is really good, but hardly a 12b ADC or as they claim for Gen3 a 14b ADC. Funny thing is that being the only player in this game they don't need to lie in marketing campaigns, but they just can't resist temptation to tell a long tale.While this device is definitely a game changer for ADI (wake up Analog Devices!) they do need to figure out how to scale down 30W of power which is mostly due to 16nm FPGA technology. They should migrate this to 7nm or 5nm ASAP and get to their end game for power efficiency. After that it is a race to ASIC (harden FPGA logic) for power and cost reduction.