PCIe 5.0
At FMS 2024, the technological requirements from the storage and memory subsystem took center stage. Both SSD and controller vendors had various demonstrations touting their suitability for different stages of the AI data pipeline - ingestion, preparation, training, checkpointing, and inference. Vendors like Solidigm have different types of SSDs optimized for different stages of the pipeline. At the same time, controller vendors have taken advantage of one of the features introduced recently in the NVM Express standard - Flexible Data Placement (FDP). FDP involves the host providing information / hints about the areas where the controller could place the incoming write data in order to reduce the write amplification. These hints are generated based on specific block sizes advertised by the device. The feature is...
The Intel Z690 Motherboard Overview (DDR4): Over 30+ New Models
To support the launch of Intel's latest 12th generation 'Alder Lake' processors, Intel has also pulled the trigger on its latest Z690 motherboard chipset. Using a new LGA1700 socket...
42 by Gavin Bonshor on 11/24/2021
The Intel Z690 Motherboard Overview (DDR5): Over 50+ New Models
To support the launch of Intel's latest 12th generation 'Alder Lake' processors, Intel has also pulled the trigger on its latest Z690 motherboard chipset. Using a new LGA1700 socket...
126 by Gavin Bonshor on 11/9/2021
Intel 12th Gen Core Alder Lake for Desktops: Top SKUs Only, Coming November 4th
Over the past few months, Intel has been drip-feeding information about its next-generation processor family. Alder Lake, commercially known as Intel’s 12th Generation Core architecture, is officially being announced...
395 by Dr. Ian Cutress on 10/27/2021
Intel Xeon Sapphire Rapids: How To Go Monolithic with Tiles
One of the critical deficits Intel has to its competition in its server platform is core count – other companies are enabling more cores by one of two routes...
99 by Dr. Ian Cutress on 8/31/2021
Update on Intel Sapphire Rapids in 2022: Q1 for Production, Q2 for Ramp, H1 Launch
In the news cycle today, Intel is announcing an update to its planned deployment of its next generation Xeon Scalable platform known as Sapphire Rapids. Sapphire Rapids is the...
34 by Dr. Ian Cutress on 6/29/2021
Marvell Announces First PCIe 5.0 NVMe SSD Controllers: Up To 14 GB/s
Today Marvell is announcing the first NVMe SSD controllers to support PCIe 5.0, and a new branding strategy for Marvell's storage controllers. The new SSD controllers are the first...
47 by Billy Tallis on 5/27/2021
Using a PCIe Slot to Install DRAM: New Samsung CXL.mem Expansion Module
In the computing industry, we’ve lived with PCIe as a standard for a long time. It is used to add any additional features to a system: graphics, storage, USB...
47 by Dr. Ian Cutress on 5/11/2021
Microchip Announces First PCIe 5.0 Switches
Building on their recent announcement of PCIe 5.0 retimers, Microchip has announced their first PCIe 5.0 switches, as part of their Switchtec PFX product line. On paper these look...
40 by Billy Tallis on 2/3/2021
Microchip Announces PCIe 5.0 And CXL Retimers
Microchip is entering the market for PCIe retimer chips with a pair of new retimers supporting PCIe 5.0's 32GT/s link speed. The new XpressConnect RTM-C 8xG5 and 16xG5 chips...
8 by Billy Tallis on 11/11/2020
Rambus Unveils PCIe 5.0 Controller & PHY
Rambus has developed a comprehensive PCIe 5.0 and CXL interface solution for chips built using 7 nm process technologies. The interface is now available for licensing by SoC designers...
17 by Anton Shilov on 11/13/2019
Gen-Z PHY Specification 1.1 Published: Adds PCIe 5.0, Gen-Z 50G Fabric
The Gen-Z Consortium this week released Physical Layer Specification 1.1 for Gen-Z interconnects. The new standard adds enhanced support for PCIe Gen 5 as well as Gen-Z 50G Fabric...
8 by Anton Shilov on 10/4/2019
Arm Joins CXL Consortium
Arm has officially joined the Compute Express Link (CXL) Consortium in a bid to enable its customers to implement the new CPU-to-Device interconnect and contribute to the specification. Arm...
7 by Anton Shilov on 9/13/2019
AMD Joins CXL Consortium: Playing in All The Interconnects
AMD's CTO, Mark Papermaster, has published a blog post this week said that AMD has joined the Compute Express Link (CXL) Consortium. The industry group is led by a...
43 by Anton Shilov on 7/19/2019
PCI-SIG Finalizes PCIe 5.0 Specification: x16 Slots to Reach 64GB/sec
Following the long gap after the release of PCI Express 3.0 in 2010, the PCI Special Interest Group (PCI-SIG) set about a plan to speed up the development and...
55 by Ryan Smith on 5/29/2019
Compute Express Link (CXL): From Nine Members to Thirty Three
Last month the CXL Specification 1.0 was released as a future cache coherent interconnect that uses the PCIe 5.0 physical infrastructure but aimed to provide a breakthrough in utility...
18 by Dr. Ian Cutress on 4/15/2019
Intel Agilex: 10nm FPGAs with PCIe 5.0, DDR5, and CXL
Ever since Intel purchased Altera for an enormous amount of money a few years ago (ed: $16.7B), the FPGA portfolio that has been coming out has largely been a...
12 by Ian Cutress on 4/2/2019
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