Merced, EPIC, & IA64 Explained

Unlike other CISC or RISC processors which generally have 32 or less registers; Merced and other EPIC processors will have 128 all-purpose registers, 128 floating point registers, and 64 predication 1bit registers. This high amount of registers will give programmers and compilers the flexibility they need with EPIC architecture. Since EPIC does a lot of operations in parallel, it needs many registers to store information in. (Since lots of data is being manipulated simultaneously.) For this reason EPIC processors provide 256+ total registers. This should be more than enough for programs to make full use of the EPIC processor and to most efficiently expose parallelism.