Original Link: https://www.anandtech.com/show/3212
About five years ago Intel introduced their (at the time) next-generation micro-architecture, what we've come to know as NetBurst. The NetBurst introduction actually took place over two IDFs, the first one was where we got brief glimpses of the new architecture and the second one where we got the full scoop on what was new. As it turns out, quite a bit was new back then, and almost all that was new has been since stripped out of the next-generation architecture that was first introduced yesterday.
Going along with history, Intel hasn't divulged too much about their next-generation architecture here at IDF, instead I'm expecting to get the rest of the story at Spring IDF 2006. That's unfortunate for those of us who want the information now, but then again we've got pretty much a full year between now and when Conroe, Merom and Woodcrest are actually released, so it isn't unreasonable. But I will say that at the very least it'd be nice for Intel to have at least released the name of the new architecture, because it's a pain writing next-generation and new architecture all the time :)
There have been some interesting morsels here at IDF already, despite the lack of information about the new architecture. If you're curious as to what they are, take a look at our IDF coverage on the front page or just head over to the Trade Shows section.
Every IDF I make it a point to stop by the Rambus booth at the Technology Showcase and say hi to a good friend, Dr. Steven Woo. We rarely talk about anything related to Rambus, but he's an incredibly bright engineer and a great person to talk to about just anything technology related.
Yesterday, on my bi-annual trip to the Rambus booth we talked a bit about Intel's new architecture. And the conversation helped me realize something, the transition to getting peak performance out of Intel's next-generation architecture may once again depend very heavily on the adaptation of Conroe/Merom/Woodcrest-friendly compilers. The idea is that it is going to be very difficult to feed a 4-issue core, and most of the code that has been compiled for the Pentium 4 or Athlon 64 won't be optimized to extract the levels of parallelism necessary for Intel's next-generation.
While I'm not sure if the battle for software optimized for Conroe/Merom/Woodcrest will be as tough as it was with the Pentium 4, simply because we are starting with a natively much higher IPC core, there will definitely be a struggle. But thanks to the nature of the architecture, even without optimized software, it shouldn't have a problem outshining the Pentium 4 (at least better than the Pentium 4 did the Pentium III...which it didn't really at first).
The other thing that I've been thinking about is an article I did a while ago where I compared clock-for-clock performance of the Athlon 64 and the Pentium M. In that piece I came to the conclusion that at the same clock speed, the Pentium M very close to the performance of the Athlon 64, despite the fact that AMD had an on-die memory controller. Areas where FP/SSE2 performance really mattered were the places where the Pentium M didn't fare so well, although Intel hopes to address those with the improvements they've scheduled for Yonah.
So I look at Conroe, Merom and Woodcrest as faster, higher IPC versions of Yonah, which is already a higher IPC version of Dothan. Thinking of the processors that way, it looks like we may actually see some pretty serious competition from Intel at the end of next year. And with AMD having no plans to update their micro-architecture in the next 1.5 years, the race may end up getting very close by this time next year.
The first keynote of today is just starting, so I'm going to get back to paying attention. More coverage later today.
Take care.