The PCI-Express interconnect standard may be going through some major changes in the coming years, based on a new announcement from the group responsible for the standard. The PCI-SIG is announcing this morning the formation of a PCIe Optical Workgroup, whose remit will be to work on enabling PCIe over optical interfaces. And while the group is still in its earliest of stages, the ramifications for the traditionally copper-bound standard could prove significant, as optical technology would bypass some increasingly stubborn limitations of copper signaling that traditional PCIe is soon approaching.

First released in the year 2000, PCI-Express was initially developed around the use of high-density edge connectors, which are still in use to this day. The PCIe Card Electromechanical specification (CEM) defines the PCIe add in card form factors in use for the last two decades, ranging from x1 to x16 connections.

But while the PCIe CEM has seen very little change over the years – in large part to ensure backward and forward compatibility – the signaling standard itself has undergone numerous speed upgrades. Including the latest PCIe 6.0 standard, the speed of a single PCIe lane has increased by 32-fold since 2000 – and the PCI-SIG will double that once more with PCIe 7.0 in 2025. As a result of increasing the amount of data transferred per pin by such a significant amount, the literal frequency band width used by the standard has increased by a similar degree, with PCIe 7.0 set to operate at nearly 32GHz.

In developing newer PCIe standards, the PCI-SIG has worked to minimize these issues, such as by employing alternative means of signaling that don’t require higher frequencies (e.g. PCIe 6 with PAM-4), and the use of mid-route retimers along with materials improvements have helped to keep up with the higher frequencies the standard does use. But the frequency limitations of copper traces within a PCB have never been eliminated entirely, which is why in more recent years the PCI-SIG has developed an official standard for PCIe over copper cabling.

Still in the works for late this year, the PCIe 5.0/6.0 cabling standard offers the option of using copper cables to carry PCIe both within a system (internal) and between systems (external). In particular, the relatively thick copper cables have less signal loss than PCB traces, overcoming the immediate drawback of high frequency comms, which is the low channel reach (i.e. short signal propagation distance). And while the cabling standard is designed to be an alternative to the PCIe CEM connector rather than a wholesale replacement, its existence underscores the problem at hand with high frequency signaling over copper, a problem that will only get even more challenging once PCIe 7.0 is made available.


PCIe Insertion Loss Budgets Over The Years (Samtec)

And that brings us to the formation of the PCI-SIG Optical Workgroup. Like the Ethernet community, which tends to be at the forefront of high frequency signaling innovation, PCI-SIG is looking towards optical, light-based communication as part of the future for PCIe. As we’ve already seen with optical networking technology, optical comms offers the potential for longer ranges and higher data rates vis-à-vis the vastly higher frequency of light, as well as a reduction in power consumed versus increasingly power-hungry copper transmission. For these reasons, the PCI-SIG is forming an Optical Workgroup to help develop the standards needed to supply PCIe over optical connections.

Strictly speaking, the creation of a new optical standard isn’t necessary to drive PCIe over optical connections. Several vendors already offer proprietary solutions, with a focus on external connectivity. But the creation of an optical standard aims to do just that – standardize how PCIe over fiber optics would work and behave. As part of the working group announcement, the traditionally consensus-based PCI-SIG is making it clear that they aren’t developing a standard for any single optical technology, but rather they are aiming to make it technology-agnostic, allowing the spec to support a wide range of optical technologies.

But the relatively broad announcement from the PCI-SIG doesn’t just stop with optical cabling as a replacement for current copper cabling, the group is also looking at “potentially developing technology-specific form factors.” While the classic CEM connector is unlikely to go away entirely any time soon – the backwards and forwards compatibility is that important – the CEM connector is the weakest/most difficult way to deliver PCIe today. So if the PCI-SIG is thinking about new form factors, then it’s likely the Optical Workgroup will at least be looking at some kind of optical-based successor to the CEM. And if that were to come to pass, this would easily be the biggest change in the PCIe specification in its 23+ year history.

But, to be sure, if any such change were to happen, it would be years down the line. The new Optical Workgroup has yet to form, let alone set its goals and requirements. With a broad remit to make PCIe more optical-friendly, any impact from the group is several years away – presumably no sooner than making a cabling standard for PCIe 7.0, if not a more direct impact on a PCIe 8.0 specification. But it shows where PCI-SIG leadership sees the future of the PCIe standard going, assuming they can get a consensus from their members. And, while not explicated stated in the PCI-SIG’s press release, any serious use of optical PCIe in this fashion would seem to be predicated on cheap optical transceivers, i.e. silicon photonics.

In any case, it will be interesting to see what eventually comes out of the PCI-SIG’s new Optical Workgroup. As PCIe begins to approach the practical limits of copper, the future of the industry’s standard peripheral interconnect may very well be to go towards the light.

Source: PCI-SIG

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  • back2future - Thursday, August 3, 2023 - link

    if RAM-like memory isn't integrated into CPU again with HBM3& and optical (price-worthy, efficient, endurability, power for transmitter diodes add to high bandwidth setups (chipset cooling 'again'), Thunderbolt optical impact on mass consumer market?) seems more being option inside CPU and server market peripherals or (if cheap alternative to 'copper') with high isolation to interference on parallel lanes, but not necessarily on distance improvement for peripherals (because of ~equal signal transmission speed, but possibly bandwidth and latency improvement for signal data on higher clock speed and lower signal degradation because of noise?)
    CXL3.0 is based on (g&e?)PCIe6.x (server&workstation(~2024/25) market or several yrs min. for arriving on consumer desktop&mobiles(?)), and for comparison DDR DIMM's native latency is ~20ns, while CXL implementation requires tolerance to ~200ns.
  • back2future - Thursday, August 3, 2023 - link

    [ DDR5 DIMM's are getting up to ~10ns and HBM seems more towards ~100ns ]
  • TeXWiller - Thursday, August 3, 2023 - link

    It would be nice to see small, cabled EDSFF backplanes becoming a thing on workstations and gaming systems alike. Let the magic of volume manufacturing bring the price of hot-swappable, large capacity PCIe storage and plug-in accelerators down to the consumer levels.
  • LuxZg - Friday, August 4, 2023 - link

    I wonder if it could be cheaper than tracing on motherboard... Or am I the only one envisioning smaller MBO, with 6-8 optical connector somewhere near CPU/chipset, bypassing ATX sizes for ITX, replacing PCIe x1-x16 slots with something thin and light, and allowing us to place hardware wherever we want in some new weird cases? Sure, we have x16 ribbons and similar, but I'd gladly switch that to something as thin as fiber cable or even if it ends up as "thick" as SATA. Then play around with free-form placing of components.

    I know I know, I'm letting my imagination go wild 😂 these connectors would probably add another 300$ to average MBO, even if it was actually cents in manufacturing, just because...
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